DIGITAL I/O
Number of channel:
32, per group (8-channel) input/output direction selectable logic levels: 1.8 V, 2.5 V, 3.3 V (software selectable)
Power Up status: All digital inputs
Impedance:
-Input: 10 kÙ
-Output: 50 Ù
Digital logic levels:
- Input high voltage: 2-5.25 V
- Input low voltage: 0-0.8 V
- Output high voltage: 2.7 V maximum
- Output low voltage: 0.5 V maximum
Input Protection: -1 to 6 V
Data Transfer:
Programmable I/O, bus-mastering
DMA with scatter-gather
Maximum Data Transfer: 200 MB/s
Digital Logic Levels:
CLOCKING MODE
Internal clock: Max. 50 MHz (100 MHz / N; 2<N<65535)
External Clock: Max. 100 MHz (support 8/16-bit data width only, data throughput must be less than 200 MB/s)
Handshaking
Burst Handshaking
TRIGGER SOURCES
Software trigger
External digital trigger: AFI[0...7]
TRIGGER MODES
Post Trigger, Retrigger, Pattern Match, handshaking
CHANGE OF STATE INTERRUPT
Interrupt Sources: Any of 32 channels or a pre-defined channel Change-of-State
APPLICATION FUNCTION I/O
Number of channels: 8
Supporting Modes: static I/O, I2C or SPI master node, external clock input/output, external digital trigger input, handshaking
